1. Field of the Invention
The present invention generally relates to a test mode control device using a nonvolatile ferroelectric memory, and more specifically, to a technique for changing a reference voltage and timing regulated for memory cell test according to a command signal.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
An extra test mode set method is required in order to test characteristics of the conventional nonvolatile ferroelectric memory in various regions. That is, in order to test only characteristics of a cell array, a level of a sensing reference voltage is manually regulated from outside of a chip. Additionally, in order to analyze characteristics of the cell array quantitatively, the sensing reference voltage is set to have a predetermined level.
In order to set a sensing reference voltage level of the conventional nonvolatile ferroelectric memory, characteristics of the chip are evaluated by using additional masks. Then, the evaluation result is fed back, and masks of corresponding layers are changed, thereby embodying the chip.
However, additional masks and wafer processes are required to set the test mode, which results in loss of cost and time.
Meanwhile, in order to embody various package types in the test of nonvolatile ferroelectric memory, various types of pad arrangement structure are required. Also, additional physical masks and wafer processes are required to change the arrangement structure of pads when the test mode of memory is set.
In this package condition, separate mask sets for package type are required, which results in loss in cost and time. Therefor, the yield is degraded.